The present invention is directed to testing digital logic such as is found in data processing systems and apparatus. More specifically, the invention relates to a scan control apparatus that produces sequences of test patterns that are shifted ("scanned") into and out of the digital logic, producing result signatures from which can be determined whether or not the digital logic will function without fault.
Digital or logic systems have often been tested by applying a variety of test signals to the system and monitoring the output signals produced in response. Adding to this technique, logic systems have also been designed to incorporate elemental memory stages (i.e., flipflops) that can be selected to function in one of two modes: A first mode in which they operate normally within the system as flipflops, registers, and other elemental memory stages, and a second mode in which a number of the memory stages are connected in series to form an extended shift register or, as more commonly referred to a, "scan line." Bit patterns are then scanned into and out of the scan lines, the output being analyzed (usually by comparing them to known or standard patterns), to determine the operability of the stages and interconnections of the tested logic.
Often microprocessors were used to control the testing, including forming the bit patterns that are scanned into the scan lines and retrieving and storing the results produced by the scanning. Usually, such testing will produce large amounts of output data, requiring large amounts of storage area to keep the test information passed through the scan lines for later analysis. For this reason, only a limited number of bit patterns are used to limit the amount of memory used for storing test information, thereby limiting the testing that could be done.
Additionally, presently known test techniques of this type were not capable of in-line testing (i.e., executing a test during operation of the system without terminating that operation). Usually, the system was halted before testing could be conducted, and then restarted after testing was completed.
Further, prior methods of scan testing were performed in a manner that allowed a relatively significant time (in terms of processor time) to elapse between the installation of the bit pattern and any operational steps that passed that bit pattern through one or more circuit stages of the system. Accordingly, tests of this type were often unable to catch those most difficult of all problems to trace: Timing or race problems within the processor system.
Accordingly, it can be seen that apparatus is needed capable of exercising a digital system, such as a processor or other logic, as completely as possible. The apparatus should be able to perform its test upon the system in a manner that is quick and transparent, disturbing the system operation as little as possible, and should also operate in a manner that will detect such "run time" errors as race and timing problems.